ESOS32
ESOSOn32-bitProcessors
esos_hwxxx_irq.h
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1 /*
2  * "Copyright (c) 2019 J. W. Bruce ("AUTHOR(S)")"
3  * All rights reserved.
4  * (J. W. Bruce, jwbruce_AT_tntech.edu, Tennessee Tech University)
5  *
6  * Permission to use, copy, modify, and distribute this software and its
7  * documentation for any purpose, without fee, and without written agreement is
8  * hereby granted, provided that the above copyright notice, the following
9  * two paragraphs and the authors appear in all copies of this software.
10  *
11  * IN NO EVENT SHALL THE "AUTHORS" BE LIABLE TO ANY PARTY FOR
12  * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
13  * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE "AUTHORS"
14  * HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
15  *
16  * THE "AUTHORS" SPECIFICALLY DISCLAIMS ANY WARRANTIES,
17  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
18  * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
19  * ON AN "AS IS" BASIS, AND THE "AUTHORS" HAS NO OBLIGATION TO
20  * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS."
21  *
22  * Please maintain this header in its entirety when copying/modifying
23  * these files.
24  *
25  *
26  */
27 
35 /************************************************************************
36  * esos_hwxxx_irq.h
37  ************************************************************************
38  * User-supplied include file which defines the IRQ which are supported
39  *
40  * NOTE: the file must be consistent with esos_hwxxx_irq.c which uses
41  * many of these constant to manipulate IRQ registers
42  */
43 
44 #ifndef ESOS_HWXXX_IRQ_H
45 #define ESOS_HWXXX_IRQ_H
46 
47 #include "esos.h"
48 #include "esos_irq.h"
49 #include "esos_hwxxx.h"
50 
51 
75 #define ESOS_USER_INTERRUPT(desc) __xESOS_USER_ISR(desc)
76 #define __xESOS_USER_ISR(attrib, ivt, ifsr, ifsb, ipcr, ipcb) void _ISRFAST attrib (void)
77 
78 
79 
80 /*
81  * Define the ESOS user IRQ levels here
82  * ESOS-based IRQs will run at IRQ priority levels
83  * 7 and 5.
84  *
85  * NOTE: Any user IRQ with its IRQ priority level at 0 signifies
86  * that the IRQ is not registered with ESOS.
87  */
93 #define ESOS_USER_IRQ_LEVEL1 6
94 
99 #define ESOS_USER_IRQ_LEVEL2 4
100 
105 #define ESOS_USER_IRQ_LEVEL3 3
106 
111 #define ESOS_USER_IRQ_LEVEL4 2
112 
113 #define __ESOS_USER_IRQ_UNREGISTERED 0
114 // this #define is the IPL that will disabled all user IRQs at once
115 #define __ESOS_DISABLE_USER_IRQS_LEVEL ESOS_USER_IRQ_LEVEL2
116 // this #define is the IPL that will enabled all user IRQs at once
117 #define __ESOS_ENABLE_USER_IRQS_LEVEL __ESOS_USER_IRQ_UNREGISTERED
118 
119 /********************************************************
120 *** IRQ masks for the PIC24/dsPIC33 chips
121 ***
122 *** The old verion (<= rev 511) defined thes interrupt
123 *** based on the compiler target device. This rewrite
124 *** (6 SEPT 2014) will attempt to diagnose whether the
125 *** target devices possesses each interrupt by checking
126 *** for the existence of the appropriate interrupt flag
127 ***
128 *** TODO: make a thorough search through the datasheets
129 *** for all device families, models, etc to make
130 *** sure Microchip did NOT change the name of these
131 *** interrupt flags over the years. (They have
132 *** a nasty habit of doing that quietly when new
133 *** chips come out.)
134 ***
135 *** MNEMONIC C30 ISR ATTRIB, IVT addr, IFS register, IFS bit, IPC register, IPC bit
136 *** see Interrupt Vector Details table in FRM or datasheets
137 *********************************************************/
138 
139 /**********************************************************************
140 *** EXTERNAL ASYNCHRONOUS INTERRUPTS
141 **********************************************************************/
142 #if (defined(_INT0IF))
143 
157 #define ESOS_IRQ_HWXXX_INT0 _INT0Interrupt, 0x0014, 0, 0, 0, 0 // external interrupt 0
158 #endif
159 
160 #if (defined(_INT1IF))
161 
175 #define ESOS_IRQ_HWXXX_INT1 _INT1Interrupt, 0x003C, 1, 4, 5, 0 // external interrupt 1
176 #endif
177 
178 #if (defined(_INT2IF))
179 
193 #define ESOS_IRQ_HWXXX_INT2 _INT2Interrupt, 0x004E, 1, 13, 7, 4 // external interrupt 2
194 #endif
195 
196 #if (defined(_INT3IF))
197 
211 #define ESOS_IRQ_HWXXX_INT3 _INT3Interrupt, 0x007E, 3, 5, 13, 4 // external interrupt 3
212 #endif
213 
214 #if (defined(_INT4IF))
215 
229 #define ESOS_IRQ_HWXXX_INT4 _INT4Interrupt, 0x0080, 3, 6, 13, 8 // external interrupt 4
230 #endif
231 
232 /**********************************************************************
233 *** INPUT CAPTURES
234 **********************************************************************/
235 #if (defined(_IC1IF))
236 
250 #define ESOS_IRQ_HWXXX_IC1 _IC1Interrupt, 0x0016, 0, 1, 0, 4 // Input capture channel 1
251 #endif
252 
253 #if (defined(_IC2IF))
254 
268 #define ESOS_IRQ_HWXXX_IC2 _IC2Interrupt, 0x001E, 0, 5, 1, 4 // Input capture channel 2
269 #endif
270 
271 
272 #if (defined(_IC3IF))
273 
287 #define ESOS_IRQ_HWXXX_IC3 _IC3Interrupt, 0x005E, 2, 5, 9, 4 // Input Capture 3
288 #endif
289 
290 #if (defined(_IC4IF))
291 
305 #define ESOS_IRQ_HWXXX_IC4 _IC4Interrupt, 0x0060, 2, 6, 9, 8 // Input Capture 4
306 #endif
307 
308 #if (defined(_IC5IF))
309 
323 #define ESOS_IRQ_HWXXX_IC5 _IC5Interrupt, 0x0062, 2, 7, 9, 12 // Input capture channel 5
324 #endif
325 
326 #if (defined(_IC6IF))
327 
341 #define ESOS_IRQ_HWXXX_IC6 _IC6Interrupt, 0x0064, 2, 8, 10, 0 // Input capture channel 6
342 #endif
343 
344 #if (defined(_IC7IF))
345 
359 #define ESOS_IRQ_HWXXX_IC7 _IC7Interrupt, 0x0040, 1, 6, 5, 8 // Input capture channel 7
360 #endif
361 
362 #if (defined(_IC8IF))
363 
377 #define ESOS_IRQ_HWXXX_IC8 _IC8Interrupt, 0x0042, 1, 7, 5, 12 // Input capture channel 8
378 #endif
379 
380 #if (defined(_IC9IF))
381 
395 #define ESOS_IRQ_HWXXX_IC9 _IC9Interrupt, 0x00CE, 5, 13, 23, 4 // Input capture channel 9
396 #endif
397 
398 #if (defined(_IC10IF))
399 
413 #define ESOS_IRQ_HWXXX_IC10 _IC10Interrupt, 0x0010E, 7, 13, 31, 4 // Input capture channel 10
414 #endif
415 
416 #if (defined(_IC11IF))
417 
431 #define ESOS_IRQ_HWXXX_IC11 _IC11Interrupt, 0x0112, 7, 15, 31, 12 // Input capture channel 11
432 #endif
433 
434 #if (defined(_IC12IF))
435 
449 #define ESOS_IRQ_HWXXX_IC12 _IC12Interrupt, 0x0116, 8, 1, 32, 4 // Input capture channel 12
450 #endif
451 
452 #if (defined(_IC13IF))
453 
467 #define ESOS_IRQ_HWXXX_IC13 _IC13Interrupt, 0x0122, 8, 7, 33, 12 // Input capture channel 13
468 #endif
469 
470 #if (defined(_IC14IF))
471 
485 #define ESOS_IRQ_HWXXX_IC14 _IC14Interrupt, 0x0126, 8, 9, 34, 4 // Input capture channel 14
486 #endif
487 
488 #if (defined(_IC15IF))
489 
503 #define ESOS_IRQ_HWXXX_IC15 _IC15Interrupt, 0x012A, 8, 11, 34, 12 // Input capture channel 15
504 #endif
505 
506 #if (defined(_IC16IF))
507 
521 #define ESOS_IRQ_HWXXX_IC16 _IC16Interrupt, 0x012E, 8, 13, 35, 4 // Input capture channel 16
522 #endif
523 
524 /**********************************************************************
525 *** OUTPUT COMPARES
526 **********************************************************************/
527 #if (defined(_OC1IF))
528 
542 #define ESOS_IRQ_HWXXX_OC1 _OC1Interrupt, 0x0018, 0, 2, 0, 8 // Output compare channel 1
543 #endif
544 
545 #if (defined(_OC2IF))
546 
560 #define ESOS_IRQ_HWXXX_OC2 _OC2Interrupt, 0x0020, 0, 6, 1, 8 // Output compare channel 2
561 #endif
562 
563 #if (defined(_OC3IF))
564 
578 #define ESOS_IRQ_HWXXX_OC3 _OC3Interrupt, 0x0046, 1, 9, 6, 4 // Output Compare 3
579 #endif
580 
581 #if (defined(_OC4IF))
582 
596 #define ESOS_IRQ_HWXXX_OC4 _OC4Interrupt, 0x0048, 1, 10, 6, 8 // Output Compare 4
597 #endif
598 
599 #if (defined(_OC5IF))
600 
614 #define ESOS_IRQ_HWXXX_OC5 _OC5Interrupt, 0x0066, 2, 9, 10, 4 // Output compare channel 5
615 #endif
616 
617 #if (defined(_OC6IF))
618 
632 #define ESOS_IRQ_HWXXX_OC6 _OC6Interrupt, 0x0068, 2, 10, 10, 8 // Output compare channel 6
633 #endif
634 
635 #if (defined(_OC7IF))
636 
650 #define ESOS_IRQ_HWXXX_OC7 _OC7Interrupt, 0x006A, 2, 11, 10, 12 // Output compare channel 7
651 #endif
652 
653 #if (defined(_OC8IF))
654 
668 #define ESOS_IRQ_HWXXX_OC8 _OC8Interrupt, 0x006C, 2, 12, 11, 0 // Output compare channel 8
669 #endif
670 
671 #if (defined(_OC9IF))
672 
686 #define ESOS_IRQ_HWXXX_OC9 _OC9Interrupt, 0x00CC, 5, 12, 23, 0 // Output compare channel 9
687 #endif
688 
689 #if (defined(_OC10IF))
690 
704 #define ESOS_IRQ_HWXXX_OC10 _OC10Interrupt, 0x010C, 7, 12, 31, 0 // Output compare channel 10
705 #endif
706 
707 #if (defined(_OC11IF))
708 
722 #define ESOS_IRQ_HWXXX_OC11 _OC11Interrupt, 0x0110, 7, 14, 31, 8 // Output compare channel 11
723 #endif
724 
725 #if (defined(_OC12IF))
726 
740 #define ESOS_IRQ_HWXXX_OC12 _OC12Interrupt, 0x0114, 8, 0, 32, 0 // Output compare channel 12
741 #endif
742 
743 #if (defined(_OC13IF))
744 
758 #define ESOS_IRQ_HWXXX_OC13 _OC13Interrupt, 0x0120, 8, 6, 33, 8 // Output compare channel 13
759 #endif
760 
761 #if (defined(_OC14IF))
762 
776 #define ESOS_IRQ_HWXXX_OC14 _OC14Interrupt, 0x0124, 8, 8, 34, 0 // Output compare channel 14
777 #endif
778 
779 #if (defined(_OC15IF))
780 
794 #define ESOS_IRQ_HWXXX_OC15 _OC15Interrupt, 0x0128, 8, 10, 34, 8 // Output compare channel 15
795 #endif
796 
797 #if (defined(_OC16IF))
798 
812 #define ESOS_IRQ_HWXXX_OC16 _OC16Interrupt, 0x012C, 8, 12, 35, 0 // Output compare channel 16
813 #endif
814 
815 /**********************************************************************
816 *** TIMERS
817 **********************************************************************/
818 // NOTE: TIMER 1 interrupt descriptor is NOT defined as ESOS
819 // uses this timer for the system tick!
820 
821 #if (defined(_T2IF))
822 
836 #define ESOS_IRQ_HWXXX_T2 _T2Interrupt, 0x0022, 0, 7, 1, 12 // Timer 2
837 #endif
838 
839 #if (defined(_T3IF))
840 
854 #define ESOS_IRQ_HWXXX_T3 _T3Interrupt, 0x0024, 0, 8, 2, 0 // Timer 3
855 #endif
856 
857 #if (defined(_T4IF))
858 
872 #define ESOS_IRQ_HWXXX_T4 _T4Interrupt, 0x004A, 1, 11, 6, 12 // Timer4
873 #endif
874 
875 #if (defined(_T5IF))
876 
890 #define ESOS_IRQ_HWXXX_T5 _T5Interrupt, 0x004C, 1, 12, 7, 0 // Timer5
891 #endif
892 
893 #if (defined(_T6IF))
894 
908 #define ESOS_IRQ_HWXXX_T6 _T6Interrupt, 0x0072, 2, 15, 11, 12 // Timer 6
909 #endif
910 
911 #if (defined(_T7IF))
912 
926 #define ESOS_IRQ_HWXXX_T7 _T7Interrupt, 0x0074, 3, 0, 12, 0 // Timer 7
927 #endif
928 
929 #if (defined(_T8IF))
930 
944 #define ESOS_IRQ_HWXXX_T8 _T8Interrupt, 0x007A, 3, 3, 12, 12 // Timer 8
945 #endif
946 
947 #if (defined(_T9IF))
948 
962 #define ESOS_IRQ_HWXXX_T9 _T9Interrupt, 0x007C, 3, 4, 13, 0 // Timer 9
963 #endif
964 
965 /**********************************************************************
966 *** DMA CHANNELS
967 **********************************************************************/
968 #if (defined(_DMA0IF))
969 
983 #define ESOS_IRQ_HWXXX_DMA0 _DMA0Interrupt, 0x001A, 0, 4, 1, 0 // DMA Channel 0
984 #endif
985 
986 #if (defined(_DMA1IF))
987 
1001 #define ESOS_IRQ_HWXXX_DMA1 _DMA1Interrupt, 0x0030, 0, 14, 3, 8 // DMA Channel 1
1002 #endif
1003 
1004 #if (defined(_DMA2IF))
1005 
1019 #define ESOS_IRQ_HWXXX_DMA2 _DMA2Interrupt, 0x0044, 1, 8, 6, 0 // DMA Channel 2
1020 #endif
1021 
1022 #if (defined(_DMA3IF))
1023 
1037 #define ESOS_IRQ_HWXXX_DMA3 _DMA3Interrupt, 0x005C, 2, 4, 9, 0 // DMA Channel 3
1038 #endif
1039 
1040 #if (defined(_DMA4IF))
1041 
1055 #define ESOS_IRQ_HWXXX_DMA4 _DMA4Interrupt, 0x0070, 2, 14, 11, 8 // DMA Channel 4
1056 #endif
1057 
1058 #if (defined(_DMA5IF))
1059 
1073 #define ESOS_IRQ_HWXXX_DMA5 _DMA5Interrupt, 0x008E, 3, 13, 15, 4 // DMA Channel 5
1074 #endif
1075 
1076 #if (defined(_DMA6IF))
1077 
1091 #define ESOS_IRQ_HWXXX_DMA6 _DMA6Interrupt, 0x009C, 4, 4, 17, 0 // DMA Channel 6
1092 #endif
1093 
1094 #if (defined(_DMA7IF))
1095 
1109 #define ESOS_IRQ_HWXXX_DMA7 _DMA7Interrupt, 0x009E, 4, 5, 17, 4 // DMA Channel 7
1110 #endif
1111 
1112 #if (defined(_DMA8IF))
1113 
1127 #define ESOS_IRQ_HWXXX_DMA8 _DMA8Interrupt, 0x0100, 7, 6, 29, 8 // DMA Channel 8
1128 #endif
1129 
1130 #if (defined(_DMA9IF))
1131 
1145 #define ESOS_IRQ_HWXXX_DMA9 _DMA9Interrupt, 0x0102, 7, 7, 29, 12 // DMA Channel 9
1146 #endif
1147 
1148 #if (defined(_DMA10IF))
1149 
1163 #define ESOS_IRQ_HWXXX_DMA10 _DMA10Interrupt, 0x0104, 7, 8, 30, 0 // DMA Channel 10
1164 #endif
1165 
1166 #if (defined(_DMA11IF))
1167 
1181 #define ESOS_IRQ_HWXXX_DMA11 _DMA11Interrupt, 0x0106, 7, 9, 30, 4 // DMA Channel 11
1182 #endif
1183 
1184 #if (defined(_DMA12IF))
1185 
1199 #define ESOS_IRQ_HWXXX_DMA12 _DMA12Interrupt, 0x0118, 8, 2, 32, 8 // DMA Channel 12
1200 #endif
1201 
1202 #if (defined(_DMA13IF))
1203 
1217 #define ESOS_IRQ_HWXXX_DMA13 _DMA13Interrupt, 0x011A, 8, 3, 32, 12 // DMA Channel 13
1218 #endif
1219 
1220 #if (defined(_DMA14IF))
1221 
1235 #define ESOS_IRQ_HWXXX_DMA14 _DMA14Interrupt, 0x011C, 8, 4, 33, 0 // DMA Channel 14
1236 #endif
1237 
1238 /**********************************************************************
1239 *** SERIAL PERIPHERAL INTERFACE (SPI)
1240 **********************************************************************/
1241 #if (defined(_SPI1IF))
1242 
1256 #define ESOS_IRQ_HWXXX_SPI1 _SPI1Interrupt, 0x0028, 0, 10, 2, 8 // SPI1 event
1257 
1272 #define ESOS_IRQ_HWXXX_SPI1E _SPI1ErrInterrupt, 0x0026, 0, 9, 2, 4 // SPI1 (exception) fault event
1273 #endif
1274 
1275 #if (defined(_SPI2F))
1276 
1290 #define ESOS_IRQ_HWXXX_SPI2 _SPI2Interrupt, 0x0056, 2, 1, 8, 4 // SPI2 Transfer Done
1291 
1305 #define ESOS_IRQ_HWXXX_SPI2E _SPI2ErrInterrupt, 0x0054, 2, 0, 8, 0 // SPI2 Error
1306 #endif
1307 
1308 #if (defined(_SPI3F))
1309 
1323 #define ESOS_IRQ_HWXXX_SPI3 _SPI3Interrupt, 0x00CA, 5, 11, 22, 12 // SPI3 Transfer Done
1324 
1338 #define ESOS_IRQ_HWXXX_SPI3E _SPI3ErrInterrupt, 0x00C8, 5, 10, 22, 8 // SPI3 Error
1339 #endif
1340 
1341 #if (defined(_SPI4F))
1342 
1356 #define ESOS_IRQ_HWXXX_SPI4 _SPI4Interrupt, 0x010A, 7, 11, 30, 12 // SPI4 Transfer Done
1357 
1371 #define ESOS_IRQ_HWXXX_SPI24 _SPI4ErrInterrupt, 0x0108, 7, 10, 30, 8 // SPI4 Error
1372 #endif
1373 
1374 /**********************************************************************
1375 *** UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART)
1376 **********************************************************************/
1377 // if the user is __NOT__ using the built-in ESOS comm system
1378 // but __IS__ using user IRQs, then we should define the UART
1379 // IRQs for their use
1380 #if !defined(_ESOS_HWXXX_RS232_H) || defined(__DOXYGEN__)
1381 
1396 #define ESOS_IRQ_HWXXX_U1TX _U1TXInterrupt, 0x002C, 0, 12, 3, 0 // UART1 TX event
1397 
1412 #define ESOS_IRQ_HWXXX_U1RX _U1RXInterrupt, 0x002A, 0, 11, 2, 12 // UART1 RX event
1413 
1429 #define ESOS_IRQ_HWXXX_U1E _U1ErrInterrupt, 0x0096, 4, 1, 16, 4 // UART1 Error event
1430 #endif // end of UART1 constants
1431 
1432 #if (defined(_U2TXIF))
1433 
1447 #define ESOS_IRQ_HWXXX_U2TX _U2TXInterrupt, 0x0052, 1, 15, 7, 12 // UART2 Transmitter
1448 
1462 #define ESOS_IRQ_HWXXX_U2RX _U2RXInterrupt, 0x0050, 1, 14, 7, 8 // UART2 Receiver
1463 
1477 #define ESOS_IRQ_HWXXX_U2E _U2ErrInterrupt, 0x0098, 4, 2, 16, 8 // UART2 Error Interrupt
1478 #endif
1479 
1480 #if (defined(_U3TXIF))
1481 
1495 #define ESOS_IRQ_HWXXX_U3TX _U3TXInterrupt, 0x00BA, 5, 3, 20, 12 // UART3 Transmitter
1496 
1510 #define ESOS_IRQ_HWXXX_U3RX _U3RXInterrupt, 0x00B8, 5, 2, 20, 8 // UART3 Receiver
1511 
1525 #define ESOS_IRQ_HWXXX_U3E _U3ErrInterrupt, 0x00B6, 5, 1, 20, 4 // UART3 Error Interrupt
1526 #endif
1527 
1528 #if (defined(_U4TXIF))
1529 
1543 #define ESOS_IRQ_HWXXX_U4TX _U4TXInterrupt, 0x00C6, 5, 9, 22, 4 // UART4 Transmitter
1544 
1558 #define ESOS_IRQ_HWXXX_U4RX _U4RXInterrupt, 0x00C4, 5, 8, 22, 0 // UART4 Receiver
1559 
1573 #define ESOS_IRQ_HWXXX_U4E _U4ErrInterrupt, 0x00C2, 5, 7, 21, 12 // UART4 Error Interrupt
1574 #endif
1575 
1576 /**********************************************************************
1577 *** ANALOG-TO-DIGITAL CONVERTER (A/D)
1578 **********************************************************************/
1579 #if (defined(_AD1IF))
1580 
1594 #define ESOS_IRQ_HWXXX_AD1 _ADC1Interrupt, 0x002E, 0, 13, 3, 4 // AD1 Conversion complete
1595 #endif
1596 #if (defined(_AD2IF))
1597 
1611 #define ESOS_IRQ_HWXXX_AD2 _ADC2Interrupt, 0x003E, 1, 5, 5, 4 // AD2 Conversion complete
1612 #endif
1613 
1614 /**********************************************************************
1615 *** NON-VOLATILE MEMORY (NVM) WRITE COMPLETE
1616 **********************************************************************/
1617 // TODO: create this user interrupt descriptor
1618 
1619 /**********************************************************************
1620 *** INTER-INTEGRATED CIRCUIT (I2C)
1621 **********************************************************************/
1622 #if (defined(_I2C1IF))
1623 
1637 #define ESOS_IRQ_HWXXX_MI2C1 _MI2C1Interrupt, 0x0036, 1, 1, 4, 4 // I2C1 Master event
1638 
1652 #define ESOS_IRQ_HWXXX_SI2C1 _SI2C1Interrupt, 0x0034, 1, 0, 4, 0 // I2C1 slave event
1653 #endif
1654 
1655 #if (defined(_I2C2IF))
1656 
1670 #define ESOS_IRQ_HWXXX_MI2C2 _MI2C2Interrupt, 0x0078, 3, 2, 12, 8 // I2C2 Master event
1671 
1685 #define ESOS_IRQ_HWXXX_SI2C2 _SI2C2Interrupt, 0x0076, 3, 1, 12, 4 // I2C2 slave event
1686 #endif
1687 
1688 /**********************************************************************
1689 *** COMPARATOR
1690 **********************************************************************/
1691 #if (defined(_CMIF))
1692 
1706 #define ESOS_IRQ_HWXXX_CM _CMInterrupt, 0x0038, 1, 2, 4, 8 // Comparator Combined Event
1707 #endif
1708 
1709 /**********************************************************************
1710 *** CHANGE NOTIFICATION
1711 **********************************************************************/
1712 #if (defined(_CNIF))
1713 
1727 #define ESOS_IRQ_HWXXX_CN _CNInterrupt, 0x003A, 1, 3, 4, 12 // Input Change Interrupt
1728 #endif
1729 
1730 /**********************************************************************
1731 *** ENHANCED CONTROLLER AREA NETWORK (ECAN)
1732 **********************************************************************/
1733 #if (defined(_C1IF))
1734 
1748 #define ESOS_IRQ_HWXXX_C1 _C1Interrupt, 0x005A, 2, 3, 8, 12 // CAN1 Event
1749 
1763 #define ESOS_IRQ_HWXXX_C1TX _C1TXInterrupt, 0x00A0, 4, 6, 17, 8 // CAN1 TX Data Request
1764 
1778 #define ESOS_IRQ_HWXXX_C1RX _C1RXInterrupt, 0x0058, 2, 2, 8, 8 // CAN1 RX Data Ready
1779 #endif
1780 
1781 #if (defined(_C2IF))
1782 
1796 #define ESOS_IRQ_HWXXX_C2 _C2Interrupt, 0x0084, 3, 8, 14, 0 // CAN2 Event
1797 
1811 #define ESOS_IRQ_HWXXX_C2TX _C2TXInterrupt, 0x00A2, 4, 7, 17, 12 // CAN2 TX Data Request
1812 
1826 #define ESOS_IRQ_HWXXX_C2RX _C2RXInterrupt, 0x0082, 3, 7, 13, 12 // CAN2 RX Data Ready
1827 #endif
1828 
1829 /**********************************************************************
1830 *** PARALLEL MASTER PORT (PMP)
1831 **********************************************************************/
1832 // TODO: add this user interrupt descriptor
1833 
1834 
1835 /**********************************************************************
1836 *** PULSE-WIDTH MODULATION (PWM)
1837 **********************************************************************/
1838 #if (defined(_PSEMIF))
1839 
1853 #define ESOS_IRQ_HWXXX_PSEM _PSEMInterrupt, 0x0086, 3, 9, 14, 4 // PWM Special Event Match
1854 #endif
1855 
1856 // TODO: write PSESM (PWM Secondary Special Event) interrupt descriptor
1857 
1858 #if (defined(_PWM1IF))
1859 
1873 #define ESOS_IRQ_HWXXX_PWM1 _PWM1Interrupt, 0x00D0, 5, 14, 23, 8
1874 #endif
1875 
1876 #if (defined(_PWM2IF))
1877 
1891 #define ESOS_IRQ_HWXXX_PWM2 _PWM2Interrupt, 0x00D2, 5, 15, 23, 12
1892 #endif
1893 
1894 #if (defined(_PWM3IF))
1895 
1909 #define ESOS_IRQ_HWXXX_PWM3 _PWM3Interrupt, 0x00D4, 6, 0, 24, 0
1910 #endif
1911 
1912 #if (defined(_PWM4IF))
1913 
1927 #define ESOS_IRQ_HWXXX_PWM4 _PWM4Interrupt, 0x00D6, 6, 1, 24, 4
1928 #endif
1929 
1930 #if (defined(_PWM5IF))
1931 
1945 #define ESOS_IRQ_HWXXX_PWM5 _PWM5Interrupt, 0x00D8, 6, 2, 24, 8
1946 #endif
1947 
1948 #if (defined(_PWM6IF))
1949 
1963 #define ESOS_IRQ_HWXXX_PWM6 _PWM6Interrupt, 0x00DA, 6, 3, 24, 12
1964 #endif
1965 
1966 #if (defined(_PWM7IF))
1967 
1981 #define ESOS_IRQ_HWXXX_PWM7 _PWM7Interrupt, 0x00DC, 6, 4, 25, 0
1982 #endif
1983 
1984 /**********************************************************************
1985 *** QUADRATURE ENCODER INTERFACE (QEI)
1986 **********************************************************************/
1987 #if (defined(_QEI1IF))
1988 
2002 #define ESOS_IRQ_HWXXX_QEI1 _QEI1Interrupt, 0x0088, 3, 10, 14, 8
2003 #endif
2004 
2005 #if (defined(_QEI2IF))
2006 
2020 #define ESOS_IRQ_HWXXX_QEI2 _QEI2Interrupt, 0x00AA, 4, 11, 18, 12
2021 #endif
2022 
2023 /**********************************************************************
2024 *** UNIVERSAL SERIAL BUS (USB) ON-THE-GO (OTG)
2025 **********************************************************************/
2026 // TODO: add this user interrupt descriptor
2027 #if (defined(_USB1IF))
2028 #endif
2029 
2030 /**********************************************************************
2031 *** REAL-TIME CLOCK CALENDAR
2032 **********************************************************************/
2033 #if (defined(_RTCIF))
2034 
2048 #define ESOS_IRQ_HWXXX_RTC _RTCInterrupt, 0x0090, 3, 14, 15, 8 // RTCC Interrupt
2049 #endif
2050 
2051 
2052 /**********************************************************************
2053 *** CYCLIC REDUNDANCY CHECKER (CRC)
2054 **********************************************************************/
2055 #if (defined(_CRCIF))
2056 
2070 #define ESOS_IRQ_HWXXX_CRC _CRCInterrupt, 0x009A, 4, 3, 16, 12 // CRC Generator Interrupt
2071 #endif
2072 
2073 #if 0
2074 // some missing interrupts
2075 DCIE
2076 DCI
2077 
2078 // some leftover interrupt descriptors from the change (JWB -- 6 SEPT 2014)
2079 #define ESOS_IRQ_HWXXX_CRC _CRCInterrupt, 0x009A, 4, 3, 16, 12 // CRC Generator Interrupt
2080 #define ESOS_IRQ_HWXXX_CTMU _CTMUInterrupt, 0x00AE, 4, 13, 19, 4 // CTMU Interrupt
2081 #define ESOS_IRQ_HWXXX_ICD _ICDInterrupt, 0x0142, 8, 14, 35, 8 // ICD Application
2082 #define ESOS_IRQ_HWXXX_JTAG _JTAGInterrupt, 0x0130, 8, 15, 35, 12 // JTAG Programming
2083 #define ESOS_IRQ_HWXXX_PTGSTEP _PTGSTEPInterrupt, 0x0136, 9, 1, 36, 4 // PTG Step
2084 #define ESOS_IRQ_HWXXX_PTGWDT _PTGWDTInterrupt, 0x0138, 9, 2, 36, 8 // PTG Watchdog Time-out
2085 #define ESOS_IRQ_HWXXX_PTG0 _PTG0Interrupt, 0x013A, 9, 3, 36, 12 // PTG Interupt 0
2086 #define ESOS_IRQ_HWXXX_PTG1 _PTG1Interrupt, 0x013C, 9, 4, 37, 0 // PTG Interrupt 1
2087 #define ESOS_IRQ_HWXXX_PTG2 _PTG2Interrupt, 0x013E, 9, 5, 37, 4 // PTG Interrupt 2
2088 #define ESOS_IRQ_HWXXX_PTG3 _PTG3Interrupt, 0x0140, 9, 6, 37, 8 // PTG Interrupt 3
2089 #endif
2090 
2091 /*
2092  * MACROs COMMON TO ALL PIC24 PROCESSORS
2093  */
2094 
2095 #define __GET_IRQ_ATTRIB(Q) __xGET_IRQ_ATTRIB(Q)
2096 #define __GET_IVTQ(Q) __xGET_IVT(Q)
2097 #define __GET_IFS_NUM(Q) __xGET_IFS_NUM(Q)
2098 #define __GET_IFS_BITNUM(Q) __xGET_IFS_BITNUM(Q)
2099 #define __GET_IEC_NUM(Q) __xGET_IFS_NUM(Q)
2100 #define __GET_IEC_BITNUM(Q) __xGET_IFS_BITNUM(Q)
2101 #define __GET_IPC_NUM(Q) __xGET_IPC_NUM(Q)
2102 #define __GET_IPC_BITNUM(Q) __xGET_IPC_BITNUM(Q)
2103 
2104 #define __xGET_IRQ_ATTRIB(attrib, ivt, ifsr, ifsb, ipcr, ipcb) attrib
2105 #define __xGET_IVT(attrib, ivt, ifsr, ifsb, ipcr, ipcb) ivt
2106 #define __xGET_IFS_NUM(attrib, ivt, ifsr, ifsb, ipcr, ipcb) ifsr
2107 #define __xGET_IFS_BITNUM(attrib, ivt, ifsr, ifsb, ipcr, ipcb) ifsb
2108 #define __xGET_IEC_NUM(attrib, ivt, ifsr, ifsb, ipcr, ipcb) ifsr
2109 #define __xGET_IEC_BITNUM(attrib, ivt, ifsr, ifsb, ipcr, ipcb) ifsb
2110 #define __xGET_IPC_NUM(attrib, ivt, ifsr, ifsb, ipcr, ipcb) ipcr
2111 #define __xGET_IPC_BITNUM(attrib, ivt, ifsr, ifsb, ipcr, ipcb) ipcb
2112 
2113 
2114 // this macro gets the IRQ's IPL number from its corresponding IPC register
2115 #define __GET_IPL_FROM_IPCX(Q) ((*(&IPC0+(__xGET_IPC_NUM(Q))) >> __xGET_IPC_BITNUM(Q))&0x7)
2116 
2117 // this macro tests the IRQ's IPL number from its corresponding IPC register
2118 // against a value
2119 #define __IS_IPL_FROM_IPCX(Q, val) ((__GET_IPL_FROM_IPCX(Q))==(val))
2120 
2121 // this macro sets the IRQ's IPL number in its corresponding IPC register
2122 #define __PUT_IPL_INTO_IPCX(ipc,ipcb,ipl) \
2123  do { \
2124  BIT_CLEAR_MASK( (*((&IPC0)+(ipc))), ((0x07<<ipcb) + (ipl<<ipcb))); \
2125  (*((&IPC0)+ipc)) += (ipl<<ipcb); \
2126  }while(0)
2127 
2144 #define ESOS_UNREGISTER_HWXXX_USER_INTERRUPT(desc) __xUNREGISTER_HWXXX_USER_INTERRUPT(desc)
2145 #define __xUNREGISTER_HWXXX_USER_INTERRUPT(attrib, ivt, ifsr, ifsb, ipcr, ipcb) \
2146  do{ \
2147  __xDISABLE_HWXXX_USER_INTERRUPT(attrib, ivt, ifsr, ifsb, ipcr, ipcb); \
2148  __PUT_IPL_INTO_IPCX(ipcr,ipcb, __ESOS_USER_IRQ_UNREGISTERED); \
2149  }while(0)
2150 
2151 
2171 #define ESOS_REGISTER_HWXXX_USER_INTERRUPT(desc, ipl, p2f) __xREGISTER_HWXXX_USER_INTERRUPT(desc, ipl, p2f)
2172 #define __xREGISTER_HWXXX_USER_INTERRUPT(attrib, ivt, ifsr, ifsb, ipcr, ipcb, ipl, p2f) \
2173  do { \
2174  __xDISABLE_HWXXX_USER_INTERRUPT(attrib, ivt, ifsr, ifsb, ipcr, ipcb); \
2175  __PUT_IPL_INTO_IPCX(ipcr, ipcb, ipl); \
2176  }while(0)
2177 
2193 #define ESOS_DISABLE_ALL_HWXXX_USER_INTERRUPTS() SET_CPU_IPL(__ESOS_DISABLE_USER_IRQS_LEVEL)
2194 
2209 #define ESOS_ENABLE_ALL_HWXXX_USER_INTERRUPTS() SET_CPU_IPL(__ESOS_ENABLE_USER_IRQS_LEVEL)
2210 
2229 #define ESOS_IS_HWXXX_USER_INTERRUPT_ENABLED(desc) __xIS_HWXXX_USER_INTERRUPT_ENABLED(desc)
2230 #define __xIS_HWXXX_USER_INTERRUPT_ENABLED(attrib, ivt, ifsr, ifsb, ipcr, ipcb) IS_BIT_SET(*(&IEC0+ifsr),ifsb)
2231 
2250 #define ESOS_DOES_HWXXX_USER_INTERRUPT_NEED_SERVICING(desc) __xDOES_HWXXX_USER_INTERRUPT_NEED_SERVICING(desc)
2251 #define __xDOES_HWXXX_USER_INTERRUPT_NEED_SERVICING(attrib, ivt, ifsr, ifsb, ipcr, ipcb) IS_BIT_SET(*(&IFS0+ifsr), ifsb)
2252 
2269 #define ESOS_MARK_HWXXX_USER_INTERRUPT_SERVICED(desc) __xMARK_HWXXX_USER_INTERRUPT_SERVICED(desc)
2270 #define __xMARK_HWXXX_USER_INTERRUPT_SERVICED(attrib, ivt, ifsr, ifsb, ipcr, ipcb) BIT_CLEAR(*(&IFS0+ifsr),ifsb)
2271 
2288 #define ESOS_ENABLE_HWXXX_USER_INTERRUPT(desc) __xENABLE_HWXXX_USER_INTERRUPT(desc)
2289 #define __xENABLE_HWXXX_USER_INTERRUPT(attrib, ivt, ifsr, ifsb, ipcr, ipcb) BIT_SET(*(&IEC0+ifsr), ifsb)
2290 
2307 #define ESOS_DISABLE_HWXXX_USER_INTERRUPT(desc) __xDISABLE_HWXXX_USER_INTERRUPT(desc)
2308 #define __xDISABLE_HWXXX_USER_INTERRUPT(attrib, ivt, ifsr, ifsb, ipcr, ipcb) BIT_CLEAR(*((&IEC0)+ifsr), ifsb)
2309 
2310 #endif // ESOS_HWXXX_IRQ_H
2311 
2312 
esos_irq.h
esos_hwxxx.h
This is the master include file template for the target hardware (hwxxxx)
esos.h
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